Designers of microprocessors and other high performance electronic devices such as communication systems and high frequency application specific integrated circuits (ASICs) are continually improving the throughput and performance of such devices by increasing internal operating frequencies. These high performance electronic devices and systems usually contain digital circuits which require clock signals to operate.
Forwarded clocks are used in high speed input-output (I/O) systems, such as Fully Buffered Dual In-line Memory Module (FBD) I/O systems. In these high speed I/O systems the data are frequently double pumped, meaning data are transmitted for both the rising and falling edges of a clock signal. Deviations in clock duty cycles will often cause timing errors and directly reduce the permissible data transmission-reception windows. The deviation becomes even more of an issue for high-loss interconnect-channels since the problem is often compounded by jitter. Correcting duty cycle is therefore often essential when transferring data at high speeds. Additionally, duty cycle correction is frequently needed on the receiver side to correct for distortions resulting from the interconnect channels, forwarded clock amplifiers, and clock distribution systems.
Current art Duty Cycle Correctors (DCC) in many of the FBD products today employ numerous types of classic and common circuits. Additionally, the designs usually contain several circuit blocks. For example, these circuits often contain a duty cycle detector circuit, a duty cycle corrector circuit, one or more amplifier circuits, a low swing to full swing level converter circuit, and a full to low swing converter. While these designs generally achieve good overall performance, power dissipation and the necessary silicon area required to implement such designs usually limit the use of these circuits to the I/O port level, in other words only one per port. In many instances, it would be beneficial to place DCC circuits in every transmit data line of a high-speed I/O bus, but as noted above power and area usually precluded such usage. Duty cycle correction circuits which require small silicon areas and consume less quantities of power are needed.